1. Field of the Invention
The present invention relates to a method and circuit for elastic storing, and more particularly to a method and circuit for elastic storing that is capable of adapting to high-speed data communications.
2. Discussion of the Background
A conventional buffering circuit which is sometimes called an elastic storing memory is shown in FIG. 1, which accommodates a difference between an external data receiving rate and an internal data reading rate.
As shown in FIG. 1, the conventional buffering circuit includes a two-port memory 201, a write address generator 202, a read address generator 203, a subtracter 204, and an address proximity detector 205. The subtracter 204 includes a decoder 204a. The write address generator 202 generates write addresses WADD for writing write data WDATA in synchronism with a write clock signal WCLK and outputs such write addresses WADD to the two-port memory 201. The read address generator 203 generates read addresses RADD for reading read data RDATA in synchronism with a read clock signal RCLK and outputs such read addresses signals RADD to the two-port memory 201.
As mentioned above, the write address generator 202 and the read address generator 203 operate in synchronism with the clock signals WCLK and RCLK different from each other. Data reading is generally started upon a completion of writing a predetermined amount of data into the two-port memory 201. If a frequency of the read clock signal RCLK is higher than a frequency of the write clock signal WCLK, a reading operation is faster than a writing operation and, as time passes, the read addresses RADD come closer from behind to the write addresses WADD. On the other hand, if a frequency of the write clock signal WCLK is higher than a frequency of the read clock signal RCLK, a writing operation is faster than a reading operation and, as time passes, the two-port memory 201 falls into an over flow state.
The subtracter 204 decodes a write address WADD and a read address RADD at a time by using the decoder 204a into respective values comparable to each other and calculates a distance of address between the write address WADD and the read address RADD, that is, a difference of the addresses within an address space of the two-port memory 201. A resultant signal is sent to the address proximity detector 205. The address proximity detector 205 compares the distance calculated by the subtracter 204 with a predetermined value. When the calculated distance is determined as being equal to the predetermined value, the address proximity detector 205 outputs a reset signal to the write address generator 202 and the read address generator 203 so as to initialize timings of the address signals from the write address generator 202 and the read address generator 203.
As the data communications rate is increasingly enhanced, an issue is made apparent on a time period for calculations, such as the distance subtraction by the subtracter 204 and the address comparison by the address proximity detector 205.
One attempt provides an elastic storing circuit which focuses on a specific portion of an address region in the two-port memory to predict a possible collision between the write address and the read address based on a relationship of position between the write address and the read address in the specific portion of the address region in the two-port memory. In accordance with the prediction, this elastic storing circuit outputs a reset signal to the write address generator and the read address generator. While it reduces an amount of addresses to be monitored by focusing on only a portion of the address region in the two-port memory, the elastic storing circuit according to this attempt produces the reset signal a number of times greater than that produced by the background buffering circuit of FIG. 1 in which the reset signal is output only immediately before a collision between the write address WADD and the read address RADD occurs. As a result, the elastic storing circuit of this attempt may bring about a delay in the processing speed.